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| order this document by mc33218a/d device operating temperature range package semiconductor technical data dw suffix plastic package case 751e voice switched speakerphone with m processor interface pin connections ordering information MC33218ADW mc33218ap t a = 40 to +85 c so24l plastic dip 24 1 p suffix plastic package case 724 24 1 cp2 1 24 (top view) v cc 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 xdi cpt tli tlo v b c t cd nc cpr rli rlo tao mco mci por dr data clk rxi rxo rao gnd 1 motorola analog ic device data
the motorola mc33218a voice switched speakerphone circuit incorporates the necessary amplifiers, attenuators, level detectors, and control algorithm to form the heart of a high quality handsfree speakerphone system. included are a microphone amplifier with mute, transmit and receive attenuators, a background monitoring system for both the transmit and receive paths, and level detectors for each path. an agc system reduces the receive gain on long lines where loop current and power are in short supply. a dial tone detector prevents fading of dial tone. a chip disable pin permits conserving power when the circuit is not in use. additionally, the mc33218a has a serial data port which permits microprocessor control of the receive volume level, microphone mute, attenuator range, and selection of transmit, receive, idle or normal modes. the data port can be operated at up to 1.0 mhz. the mc33218a can be operated from a power supply, or from the telephone line, requiring typically 4.6 ma. it can be used in conjunction with a variety of speech networks. applications include not only speakerphones, but intercoms and other voice switched devices. ? supply voltage range: 2.7 to 6.5 v ? attenuator range: 53 or 27 db (selectable) ? 2 point sensing with background noise monitor in each path ? microprocessor port for control of: volume control (40 db range over 16 levels) mute microphone amplifier force to receive, transmit, or idle modes attenuator range selection (27 or 53 db) ? chip disable pin powers down the entire ic ? 24 pin narrow body (300 mil) dip and 24 pin soic this document contains information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 1995 simplified block diagram this device contains 610 active transistors. microphone transmit out v b v b v b v b v b bnm reg. r x attenuator mc33218a v cc t x attenuator attenuator control dtd speaker amplifier speaker cd receive in bnm dr data por clk serial port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 2 motorola analog ic device data maximum ratings rating symbol min max unit supply voltage v cc 0.5 7.0 vdc any input v in 0.4 v cc + 0.4 vdc maximum junction temperature t j +150 c storage temperature range t stg 65 +150 c note: devices should not be operated at or outside these values. the arecommended operating limitso provide for actual device operation. recommended operating limits characteristic symbol min typ max unit supply voltage (nonagc range) v cc 3.5 6.5 vdc (agc range) 2.7 3.5 maximum attenuator input signal v in(max) 300 mvrms logic input voltage (pins 8, 1719) v inl vdc low 0 0.8 high 2.0 v cc clock and data rate (serial port) f data 0 1.0 mhz v b output current i vb see figure 14 ma operating ambient temperature range t a 40 +85 c electrical characteristics (t a = + 25 c, v cc = 5.0 v, cd 0.8 v, unless noted, see figure 3.) characteristic symbol min typ max unit power supply supply current (enabled, cd 0.8, v b open, see figure 13) i cce ma idle mode 3.0 4.6 6.0 t x mode 4.6 r x mode 5.3 supply current (disabled, cd = 2.0 v, v b open) i ccd m a v cc = 3.0 v 67 v cc = 5.0 v 50 110 170 v cc = 6.5 v 150 v b output voltage (i vb = 0, cd = 0) v b vdc v cc = 2.7 v 0.9 v cc = 5.0 v 2.1 2.2 2.3 v cc = 6.5 v 3.0 v b output resistance (i vb 1.0 ma) r ovb 600 w psrr @ v b versus v cc , f = 1.0 khz, c vb = 100 m f psrr 57 db attenuator control c t voltage (with respect to v b ) v ct v b mv (full range, b5 = 0) r x mode (maximum volume) +150 (full range, b 5 = 0) idle mode 0 (full range, b 5 = 0) t x mode 100 (half range, b5 = 1) r x mode (maximum volume +85 (half range, b 5 = 1) idle mode 0 (half range, b 5 = 1) t x mode 35 c t source current (switching to r x mode) i ctr 55 42 33 m a c t sink current (switching to t x mode) i ctt 33 42 55 m a c t idle current i cti 3.0 0 3.0 m a dial tone detector threshold (with respect to v b at rxo) v dt 40 20 8.0 mv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 3 motorola analog ic device data electrical characteristics (continued) (t a = + 25 c, v cc = 5.0 v, cd 0.8 v, unless noted, see figure 3.) characteristic unit max typ min symbol attenuators receive attenuator gain (f = 1.0 khz, maximum volume) db full attenuation range (b5 = 0) r x mode g rxf 3.0 6.7 9.0 t x mode g rxtf 49 47 43 idle mode g rxif 28 25 22 range (r x to t x mode) d g rxf 50 53 56 half attenuation range (b5 = 1) r x mode g rxh 10 7.0 4.0 t x mode g rxth 37 34 31 idle mode g rxih 28 25 22 range (r x to t x mode) d g rxh 23 27 29 volume control range (r x mode only, b3b0 changed from 0000 to 1111, see figures 6, 7) v cr db full range 34 40 46 half range 25 agc attenuation range (v cc = 3.5 to 2.7 v, receive mode only, b3b0 = 0000, see figure 8) g agc db full range 12 21 28 half range 19 transmit attenuator gain (f = 1.0 khz, maximum volume) db full attenuation range (b5 = 0) t x mode g txf 3.0 6.7 9.0 r x mode g txrf 49 47 43 idle mode g txif 19 16 13 range (t x to r x mode) d g txf 50 53 56 half attenuation range (b5 = 1) t x mode g txh 9.0 6.5 3.0 r x mode g txrh 36 34 30 idle mode g txih 19 16 13 range (t x to r x mode) d g txh 23 27 29 rao, tao output current capability i oatt 2.0 ma rao offset voltage with respect to v b v rao mvdc r x mode 50 idle mode 0 t x mode 2.0 tao offset voltage with respect to v b v tao mvdc r x mode 2.0 idle mode 5.0 t x mode 50 microphone amplifier (pins 21, 22) output offset with respect to v b (rf = 300 k w ) mco vos 10 mvdc input bias current (pin 21) i mbias 30 na open loop gain (f < 100 hz) a volm 80 db gain bandwidth gbw m 1.5 mhz maximum output voltage swing (note 1) v omax 350 mvrms maximum output current capability i omco 2.0 ma muting ( d gain) microphone amplifier only (measured at pin 22) amt db rf = 300 k w 73 rf = 100 k w 64 microphone amplifier + transmit attenuator in receive mode (measured at pin 23) rf = 300 k w tmt 95 113 db note: 1. output swing is limited by the capability of the transmit attenuator input. see figure 16. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 4 motorola analog ic device data electrical characteristics (continued) (t a = + 25 c, v cc = 5.0 v, cd 0.8 v, unless noted, see figure 3.) characteristic unit max typ min symbol muting ( d gain) timing from data ready lotohi (see figure 27) m s to mute t mm 2.0 to enable t enm 1.0 receive amplifier (pins 15, 16) output offset with respect to v b (rf = 10 k w ) rxo vos 1.3 mvdc input bias current (pin 16) i rbias 30 na open loop gain (f < 100 hz) a volr 80 db gain bandwidth g bwr 1.5 mhz maximum output voltage swing (note 2) v omax 350 mvrms maximum output current capability i orxo 2.0 ma level detectors and background noise monitors t x r x switching threshold (pins 4, 11) i th 0.8 1.0 1.2 m a/ m a cpr, cpt output resistance (for pulldown) r cp 5.0 w cpr, cpt leakage current i cplk 0.2 m a cpr, cpt nominal dc voltage (no signal) v cp 1.9 vdc tlo, rlo, cp2 source current (@ v b 1.0 v) i ldoh 2.0 ma tlo, rlo, cp2 output resistance r ld 500 w tlo, rlo, cp2 sink current (@ v b + 1.0 v) i ldol 2.0 m a cd input (pin 8) switching threshold v thcd 1.5 vdc input resistance (v in = 0.8 v) r cd 170 235 300 k w input current (v in = 5.0 v) i cd 40 m a timing m s to disable t cd 3.0 to enable t enc see figure 26 por input (pin 20) switching threshold (2.7 v v cc 6.5 v) v thpor 1.2 vdc nominal dc voltage (2.7 v v cc 6.5 v) v por 1.5 vdc effective resistance (0 v < v in < 0.5 v) r por 70 115 160 k w input current i por m a v in = 0 v 40 v in = 5.0 v 630 timing to reset (pin 20 taken to < 1.2 v) t por 30 m s minimum power on reset time (see figure 20) t mpor ms c = 0.1 m f v cc = 6.5 v 2.7 c = 0.1 m f v cc = 5.0 v 3.7 c = 0.1 m f v cc = 2.7 v 10.6 note: 2. output swing is limited by the capability of the receive attenuator input. see figure 16. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 5 motorola analog ic device data electrical characteristics (continued) (t a = + 25 c, v cc = 5.0 v, cd 0.8 v, unless noted, see figure 3.) characteristic unit max typ min symbol serial port (pins 1719) switching threshold v thsp 1.3 vdc clock input current (pin 17) i inck m a dr 0.8 v v in = 0.9 v 5.6 7.5 12.8 dr 0.8 v v in = 5.0 v 75 dr 2.0 v v in = 0.6 v 5.2 7.9 13.3 dr 2.0 v v in = 5.0 v 84 data input current (pin 18) v in = 0.9 v v in = 5.0 v i inda 5.6 7.5 75 12.8 m a data ready input current (pin 19) v in = 0.9 v v in = 5.0 v i indr 13.8 20 200 36 m a timing (minimum requirements) (see figure 2) ns data ready falling edge to clock t 1 200 8th clock rising edge to dr rising edge t 2 100 data setup time t 3 100 data hold time t 4 100 clock high time t 5 200 system distortion (see figure 1) microphone amplifier + t x attenuator distortion thd t 0.2 3.0 % receive amplifier + r x attenuator distortion thd r 0.2 3.0 % figure 1. system distortion test v out v in 3.5 mv 1.0 khz v b t x attenuator 23 tao 22 21 mci mco 3.0 k 300 k note: r x attenuator forced to receive mode. note: t x attenuator forced to transmit mode. v out v in 350 mv 1.0 khz v b r x attenuator 14 rao 15 16 rxi rxo 10 k 10 k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 6 motorola analog ic device data typical temperature performance characteristics 40 c 0 c +25 c +85 c unit power supply current enabled, v b open 5.4 4.9 4.6 4.2 ma disabled, v b open 129 118 110 125 m a v b output voltage (i vb = 0) 2.0 2.15 2.2 2.3 vdc c t source current (switching to r x mode) 37 41 42 42 m a c t sink current (switching to t x mode) 36 41 42 43 m a attenuator aono gain (full range) 6.7 6.7 6.7 6.4 db attenuator range (full range) 53 53 53 53 db volume control range (r x mode only, b3b0 changed from 0000 to 1111) 36 39 40 42 db agc attenuation range 38 20 21 22 db note: temperature data is typical performance only, based on sample characterization, and does not provide guaranteed limits over temperature. pin function description pin symbol description 1 cp2 a capacitor at this pin stores voltage representing the transmit background noise and speech levels for the background noise monitor. 2 xdi input to the transmit background noise monitor. 3 cpt an rc sets the time constant for the transmit background noise monitor. 4 tli input to the transmit level detector. 5 tlo output of the transmit level detector. 6 v b a midsupply reference voltage, and analog ground for the amplifiers. this must be well bypassed for proper power supply rejection. 7 c t an rc sets the switching time between transmit, receive and idle modes. 8 cd chip disable (logic input). when low, the ic is active. when high, the entire ic is powered down and nonfunctional, except for v b . input impedance is nominally 235 k w . 9 nc no internal connection. 10 cpr an rc sets the time constant for the receive background noise monitor. 11 rli input to the receive level detector. 12 rlo output of the receive level detector. 13 gnd ground pin for the entire ic. 14 rao output of the receive attenuator. 15 rxo output of the receive path input amplifier, and input of the receive attenuator and the dial tone detector. 16 rxi inverting input of the receive amplifier. bias current flows out of the pin. 17 clk serial port clock. 1.0 mhz maximum. data is entered on clock's rising edge. 18 data serial port data input. data consists of an 8 bit word, b7 first, b0 last. 19 dr serial port data ready. taking this line high latches new data into the registers. 20 por power on reset for the serial port. upon power up, or when cd is active, all internal registers are set to logic 0. this logic input may be taken low to reset the registers. 21 mci inverting input of the microphone amplifier. bias current flows out of the pin. 22 mco output of the microphone amplifier, and input of the transmit attenuator. 23 tao output of the transmit attenuator. 24 v cc power supply pin. operating range is 2.7 v to 6.5 vdc. bypassing is requried. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 7 motorola analog ic device data figure 2. serial port timing diagram notes: 1. maximum clock and data rate is 1.0 mhz. there is no required minimum rate. 2. b7 is to be entered first, b0 last. 3. data is entered on the clock rising edge. 4. clock can continue to toggle after b0 is entered if data ready goes high before the clock's next rising edge. this is not recommended due to possible noise problems. 5. upon power up, all bits are internally set to logic 0, by the por pin. 6. data ready must go low before the first falling clock edge after the clock rising edge associated with b7. see text for additional information. b7 t 2 data ready clock data in t 5 b6 b5 b4 b3 b2 b1 b0 t 1 t 3 t 4 serial port control bits bits code function b7, b6 00 01 10 11 normal voice switched operation force to receive mode force to idle mode force to transmit mode b5 0 1 attenuator range is 53 db attenuator range is 27 db b4 0 1 microphone amplifier is active microphone amplifier is muted b3b0 (note 1) 0000 1111 maximum receive volume minimum receive volume note: 1. bit b0 is the lsb for the volume control. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 8 motorola analog ic device data figure 3. mc33218a block diagram and test circuit notes: 1. all capacitors are in m f unless otherwise noted. 2. values shown are suggested initial values only. see applications information for circuit adjustments. mc34119 speaker amplifier receive input from 24 wire converter r x attenuator attenuator control circuit t x attenuator bias agc t x bnm dial tone detector r x bnm 0.1 5.1 k r 2 10 k 10 k 0.1 1.0 47 100 k v cc 100 15 15 k 1.0 100 v b v b v th microprocessor dr disable cd v cc 0.22 from microphone transmit output to 24 wire converter 47 0.1 4.7 k 0.1 5.1 k 300 k 1.0 100 k v cc v b 6 7 5 16 15 14 11 12 10 13 24 8 18 21 22 3.0 k v b 34 2 23 1 t x r x comp. v b v cc v b clock data data register and decode logic 17 20 19 spi normal 0.1 gnd cpr rlo rli rao rxo rxi ct tlo tli cpt cp2 tao mco xdi r 1 por ck din dr mci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 9 motorola analog ic device data 35 0 100 10 attenuator gain (db) v ct v b (mv) attenuator gain (db) 0 50 50 150 100 5.0 85 45 0 10 20 30 40 10 20 30 40 50 transmit attenuator receive attenuator transmit attenuator receive attenuator v ct v b (mv) 0 10 4 8f c 0 10 20 30 50 40 receive attenuator gain (db) volume setting (bits b3b0, hex value) 0 10 4 8f c 0 10 20 30 50 40 receive attenuator gain (db) volume setting (bits b3b0, hex value) v out b , output voltage (mv) v 0 100 v in , input signal (mvrms) 60 20 0 60 20 100 2.0 m a v out 1.0 m f 500 tli rli xdi tlo rlo cp2 v in @ 1.0 khz 40 80 120 160 200 c r 2.7 10 2.9 3.1 3.5 3.3 0 10 20 30 50 40 receive attenuator gain (db) v cc (vdc) figure 4. attenuator gain versus v ct (pin 7) (full attenuator range) figure 5. attenuator gain versus v ct (half attenuation range) figure 6. receive gain versus volume control levels (full attenuation range) figure 7. receive gain versus volume control levels (half attenuation range) figure 8. receive gain versus v cc figure 9. level detector ac transfer characteristics 15 25 65 v cc 3.5 v v cc = 3.1 v v cc = 2.7 v v cc 3.5 v v cc = 3.1 v v cc = 2.7 v full range half range b3b0 = 0000 r = 5.1 k, c = 0.1 m f r = 10 k, c = 0.047 m f r = 10 k, c = 0.1 m f v b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 10 motorola analog ic device data v out b , output voltage (mv) v 100 100 f, frequency (hz) figure 10. level detector ac transfer characteristics versus frequency 300 1.0 k 10 k 20 20 60 0 0 200 v out b , output voltage (mv) figure 11. level detector dc transfer characteristics 100 0 100 150 50 i in , dc input current ( m a) 40 80 120 160 200 v input current ( a) m input voltage (v) 60 figure 12. cd input characteristics (pin 8) 40 20 0 0 1.0 2.0 3.0 5.0 7.0 4.0 6.0 valid for v in v cc 2.0 m a v out 1.0 m f 500 tli rli xdi tlo rlo cp2 i in figure 13. power supply current v b (v) 0 4.0 0 6.0 i b , output current (ma) i cc (ma) v cc (v) figure 14. v b output characteristics 3.0 2.0 1.0 5.0 3.0 2.0 0 0.5 1.0 1.5 1.0 2.0 3.0 4.0 5.0 6.0 1.0 0 4.0 7.0 200 100 psrr (db) f, frequency (hz) at v cc figure 15. v b power supply rejection versus frequency and v b capacitor 80 60 20 0 1.0 k 10 k 20 k 40 2.0 m a v out 1.0 m f 500 tli rli xdi tlo rlo cp2 v in @ 1.0 khz c 5.1 k v in = 100 mvrms v b 0.1 m f 50 v b cd 0.8 v idle mode 2.0 v cd v cc v cc = 6.5 v 150 m a v cc = 5.0 v v cc = 4.0 v v cc = 3.0 v 2.0 c vb = 1000 m f c vb = 100 m f c vb = 33 m f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 11 motorola analog ic device data 2.7 v v cc 6.5 v 2.5 v cc (v) figure 16. receive amp and microphone amp output swing 1.0 0.5 0 3.5 4.5 5.5 6.5 output swing (vrms) input current ( a) m 0 300 1.0 k 100 input voltage (v) d gain, muting (db) figure 17. microphone amplifier muting versus feedback resistor rf, feedback resistor ( w ) figure 18. serial port input characteristics (pins 17, 18, 19) 80 60 40 20 0 200 100 0 10 k 100 k 300 k 1.0 2.0 3.0 7.0 5.0 6.0 4.0 input current ( a) m 0 1000 input voltage (v) figure 19. por input characteristics (pin 20) 800 600 400 200 100 1.0 2.0 3.0 7.0 5.0 6.0 4.0 reset time (ms) 2.5 80 v cc (v) figure 20. minimum reset time versus v cc and pin 20 capacitor 60 40 20 0 3.5 4.5 5.5 6.5 thd = 5% thd 1% thd measured at tao, rao dr clk (dr = hi) data & clk (dr = lo) valid for v in v cc v cc = 3.0 v v cc = 6.5 v valid for v in v cc 0 c = 0.68 m f c = 0.022 m f c = 0.1 m f time for pin 20 to reach 1.2 v from ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 12 motorola analog ic device data figure 21. idle transmit timing ????????????? ????????????? ????????????? ???? ???? ???? ??? ??? ??? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??? ????????????? ????????????? ????????????? ????????????? ????????????? mco tao output cpt c t tlo 1.0 s 1.0 s 36 ms 420 mvrms 36 mv 200 mv 140 mv 84 mv 100 mv 240 ms 32 mvrms 85 ms 14 mvrms 200 mvrms, 1.0 khz 225 ms time constant idle t x figure 22. idle receive timing note: refer to figure 3 for component values. timing and output amplitudes shown are nominal, and are for the indicated input signal and component values. actual timing and outputs will vary with the application. bits b7, b6 = 00. ????????????? ????????????? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ????????????? ????????????? ????????????? ????????????? 610 ms 55 ms 360 mv 1.0 s 1.0 s 2.0 mvrms 200 mvrms, 1.0 khz 225 ms time constant 85 ms 150 mv 140 mv 75 ms rxo rao output cpr c t rlo 420 mvrms idle r x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 13 motorola analog ic device data figure 23. transmit receive timing (short cycle timing) note: external component values are those shown in figure 3. timing and output amplitudes shown are nominal, and are for the indicated input signal and component values. actual timing and outputs will vary with the application. bits b7, b6 = 00. 80 ms 75 ms 100 ms ????????? ????????? ?????????? ?????????? ??? ??? ?????????? ?????????? ??? ??? ??????? ??????? ??????? ??????? ??????? ??????? ?? ?? ?? ?? ????????? ????????? ????????? ????????? ??? ??? ??? ??? 300 ms 200 mvrms, 1.0 khz 300 ms 200 mvrms, 1.0 khz 200 mv 200 mv 250 mv 430 mvrms 430 mvrms 90 ms 17 ms mco tao output idle t x rxo tlo rlo c t rao output r x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 14 motorola analog ic device data figure 24. transmit receive timing (long cycle timing) ?????????? ?????????? ?????????? ?????????? ?? ?? ?????????? ?????????? ??? ??? ?? ?? ?? ?? ?????????? ?????????? ?????????? ?????????? ?? ?? ?? ?? ????? ????? ????? ?? ?? ?? ???? ???? ???? 1.0 s 200 mvrms, 1.0 khz 1.0 s 200 mvrms, 1.0 khz 200 mv 200 mv 250 mv 85 ms 75 ms 145 ms 80 ms 430 mvrms 430 mvrms 67 mvrms t1 225 ms time constant mco tao output idle t x rxo tlo rlo c t rao output r x note: external component values are those shown in figure 3. timing and output amplitudes shown are nominal, and are for the indicated input signal and component values. actual timing and outputs will vary with the application. time t1 depends on the ratio of the aono/aoffo amplitude of the signal at mco. bits b7, b6 = 00. ????? ????? ????? ?? ?? ?? ????? ????? ????? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 15 motorola analog ic device data figure 25. transmit receive timing (long cycle timing) note: external component values are those shown in figure 3, except the capacitor at c t is 6.8 m f. timing and output amplitudes shown are nominal, and are for the indicated input signal and component values. actual timing and outputs will vary with the application. time t1 depends on the ratio of the aono/aoffo amplitude of the signal at mco. bits b7, b6 = 00. ?????????? ?????????? ?????????? ?????????? ?? ?? ?????????? ?????????? ??? ??? ?? ?? ?? ?? ?????????? ?????????? ?????????? ?????????? ?? ?? ?? ?? ????? ????? ????? ?? ?? ?? ???? ???? ???? 1.0 s 200 mvrms, 1.0 khz 1.0 s 200 mvrms, 1.0 khz 200 mv 200 mv 250 mv 85 ms 27 ms 83 ms 29 ms 430 mvrms 430 mvrms 40 mvrms t1 100 ms time constant mco tao output idle t x rxo tlo rlo c t rao output r x ????? ????? ????? ?? ?? ?? ????? ????? ????? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 16 motorola analog ic device data figure 26. chip disable timing figure 27. mute timing figure 28. por timing note: above time established by first muting the microphone amplifier (b4 = 1). then the por pin is taken low. the 30 m s is representative if the internal delay for the internal registers to be reset to 0, and the associated function change. the registers will remain set to 0 when por goes high, until new data is written. t1 ????? ????? ?????????????? ?????????????? t off 3.0 m s 5.0 m s cd input (pin 8) output at rao, tao t off 10 ms 20 ms 50 ms t1 25 ms 45 ms 60 ms ????????? ????????? ????????? ?????? ?????? ?????? 2.0 m s 1.0 m s b4 = 1 b4 = 0 data ready (pin 19) output at mco 1.2 v ????????????? ????????????? ????????????? mco 30 m s por (pin 20) note: enable time t1 depends on the length of t off according to the following chart: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 17 motorola analog ic device data functional description introduction the fundamental difference between the operation of a speakerphone and a telephone handset is that of halfduplex versus fullduplex. the handset is full duplex, meaning conversation can occur in both directions (transmit and receive) simultaneously. this is possible due to both the low sound level at the receiver, and the fact that the acoustic coupling from the earpiece to the mouthpiece is almost nonexistent (the receiver is normally held against a person's ear). the loop gain from the receiver to the microphone and through the circuit is well below that needed to sustain oscillations. a speakerphone, on the other hand, has higher gain levels in both the transmit and receive paths, and attempting to converse full duplex results in oscillatory problems due to the loop that exists within the speakerphone circuit. the loop is formed by the hybrid, the acoustic coupling (speaker to microphone), and the transmit and receive paths (between the hybrid and the speaker/microphone). the only practical and economical method used to date is to design the speakerphone to function in a half duplex mode i.e., only one person speaks at a time, while the other listens. to achieve this requires a circuit which can detect who is talking (in reality, who is talking louder), switch aono the appropriate path (transmit or receive), and switch aoffo (attenuate) the other path. in this way, the loop gain is maintained less than unity. when the talkers exchange function, the circuit must quickly detect this, and switch the circuit appropriately. by providing speech level detectors, the circuit operates in a ahandsfreeo mode, eliminating the need for a apushtotalko switch. the mc33218a provides the necessary circuitry to perform a voice switched, half duplex, speakerphone function. the ic includes transmit and receive attenuators, preamplifiers, and level detectors and background noise monitors for each path. an attenuator control circuit automatically adjusts the gain of the transmit and receive attenuators based on the relative strengths of the voice signals present, the volume control, and the supply voltage (when low). the detection sensitivity and timing are externally controllable. the mc33218a is unique compared to most speakerphone integrated circuits in that it has a microprocessor serial port for control of various functions. those functions are: volume level (15 steps of 3.0 db each) microphone amplifier mute attenuator range selection (53 db or 27 db) force to receive, idle, or transmit to override the automatic switching. please refer to the block diagram (figure 3) when reading the following sections. transmit and receive attenuators (full range b5 = 0) the transmit and receive attenuators are complementary, performing a logantilog function. when one is at maximum gain ( 6.7 db), the other is at maximum attenuation ( 47 db) they are never both fully aono or fully aoffo. both attenuators are controlled by a single output from the attenuator control circuit which ensures the sum of their gains will remain constant at a typical value of 40 db. their purpose is to provide the halfduplex operation required in a speakerphone. the attenuators are noninverting, and have a usable bandwidth of 50 khz. their input signal (at mco and rxo) should be limited to 300 mvrms (850 mvpp) to prevent distortion. that maximum recommended input signal is independent of the volume control setting. both the inputs and outputs are biased at v b . the output impedance is <10 w until the output current limit (typically 2.0 ma peak) is reached. the attenuators are controlled by the single output of the attenuator control circuit, which is measurable at c t (pin 7). when the circuit detects speech signals directing it to the receive mode (by means of the level detectors described below), an internal current source of 42 m a will charge the c t capacitor to a voltage positive with respect to v b (see figure 29). at the maximum volume control setting, this voltage will be approximately +150 mv, and the receive attenuator will have a gain of + 6.7 db. when the circuit detects speech signals directing it to the transmit mode, an internal current source of 42 m a will take the capacitor to approximately 100 mv with respect to v b (the transmit attenuator will have a gain of + 6.7 db). when there is no speech present in either path, the current sources are shut off, and the voltage at c t will decay to be equal to v b . this is the idle mode, and the attenuators' gains are nearly halfway between their fully aono and fully aoffo positions ( 25 db for the r x attenuator, 16 db for the t x attenuator). monitoring the c t voltage (with respect to v b ) is the most direct method of monitoring the circuit's mode, and its response. transmit and receive attenuators (half range b5 = 1) with the attenuators set to the half range, the attenuator which is aono will have a gain of 7.0 db, while the aoffo attenuator will have a gain of 34 db. the idle mode is the same as for the full range ( 25 db for the r x attenuator, 16 db for the t x attenuator). the voltage at the c t pin, with respect to v b, will be 35 mv for the transmit mode, and + 85 mv for the receive mode. attenuator control circuit the inputs to the attenuator control section (figure 29) are six: the t x r x comparator operated by the level detectors, two background noise monitors, the agc circuit, the dialtone detector, and the microprocessor interface. these six functions are described as follows. level detectors, t x r x comparator there are two identical level detectors one on the receive side and one on the transmit side (refer to figure 30). each level detector is a high gain amplifier with backtoback diodes in the feedback path, resulting in nonlinear gain, which permits operation over a wide dynamic range of speech levels. refer to the graphs of figures 9, 10, and 11 for t heir dc and ac transfer characteristics. the sensitivity of each level detector is determined by the external resistor and capacitor at their input (tli and rli). the output charges an external capacitor through a diode and limiting resistor, thus providing a dc representation of the input ac signal level. the outputs have a quick rise time (determined by the capacitor and an internal 500 w resistor), and a slow decay time set by an internal current source and the capacitor. the capacitors at rlo and tlo should have the same value ( 10%) to prevent timing problems. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 18 motorola analog ic device data figure 29. c t attenuator control circuit v b i 1 42 m a to attenuators r t c t background monitors t x r x comp m p interface dial tone det. voltage clamps control circuit i 2 42 m a c t mc33218a agc t x r x r x t x referring to figure 3, the outputs of the two level detectors drive the t x r x comparator. the comparator's output state depends on whether the transmit or receive speech signal is stronger, as sensed by the level detectors. the attenuator control circuit uses this signal, along with the background noise monitors, to determine which mode to set. figure 30. level detector tlo (rlo) 1.0 m f 500 w 2.0 m a tli (rli) v b r c signal input external component values are application dependent. background noise monitors the purpose of a background noise monitor is to distinguish speech (which consists of bursts) from background noise (a relatively constant signal). there are two background noise monitors one for the receive path and one for the transmit path. referring to figure 32, each is operated on by a level detector, which provides a dc voltage representative of the combined speech and noise level. the peaks, valleys, and bursts, which are characteristic of speech, will cause that dc voltage (at cp2 or rlo) to increase relatively quickly, causing the output of the next amplifier to also rise quickly. if that increase exceeds the 36 mv offset, at a speed faster than the time constant at cpt (cpr), the output of the last comparator will change, indicating the presence of speech to the attenuator control circuit. this will keep the circuit in either the transmit or the receive mode, depending on which side has the stronger signals. whenever a new continuous signal is applied, the time constant at cpt (cpr) determines how long it takes the circuit to decide that the new sound is continuous, and therefore background noise. the system requires that the average speech signal be stronger than the background noise level (by 6.07.0 db) for proper speech detection to occur. when only background noise is present in both paths, the output of the monitors will indicate the absence of speech, allowing the circuit to go to the idle mode. agc circuit in the receive mode only, the agc circuit decreases the gain of the receive attenuator when the supply voltage at v cc falls below 3.5 v, according to the graph of figure 8. the gain of the transmit path changes in a complementary manner. the purpose of this feature is to reduce the power (and current) used by the speaker when the speakerphone is powered by the phone line, and is connected to a long telephone line, where the available power is limited. reducing the speaker power controls the voltage sag at v cc, reduces clipping and distortion at the speaker output, and prevents possible erratic operation. dial tone detector when a speakerphone is initially taken offhook, the dial tone signal will switch the circuit to the receive mode. however, since the dial tone is a continuous signal, the mc33218a will consider it as background noise, rather than speech, and would switch from receive to idle, causing the dial tone sound to fade. the dial tone detector prevents the fading by disabling the receive background noise monitor. the dial tone detector is a comparator with one side connected to the receive attenuator input (rxo), and the other input connected to v b with a 20 mv offset (see figure 31). if the circuit is in the receive mode, and the incoming signal has peaks greater than 20 mv (14 mv rms), the comparator's output will change, keeping the circuit from switching to the idle mode. the receive attenuator will then be at a gain determined solely by the volume control. note: the dial tone detector is not a frequency discriminating circuit. figure 31. dial tone detector to attenuator control circuit to r x attenuator v b 20 mv rxo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 19 motorola analog ic device data figure 32. background noise monitor 18.6 k 500 w xdi (rli) v b r c signal input 31.7 k v b cp2 (rlo) cpt (cpr) 2.0 m a 36 mv 47 m f 100 k to attenuator control circuit background noise monitor v cc 1.0 m f external component values are application dependent. microprocessor interface the three line spi port (pins 1719) is used for setting various functions with a single 8 bit word. the functions are as follows: volume control: bits b0b3 control the gain of the attenuators only when in the receive mode. setting b3b0 = 0000 sets the receive attenuator to its maximum gain (+ 6.7 db in full range, 7.0 db in half range), and therefore maximum volume at the speaker. setting b3b0 = 1111 sets the receive attenuator to a minimum gain level ( 32 db), and is the minimum volume setting. b0 is the lsb for this function, and each step changes the gain by 3.0 db at the high volume end (see figure 6 and 7). the transmit attenuator gain is varied in a complementary manner. these bits have no effect in the idle or transmit modes. muting of the microphone amplifier: bit b4 is used to set the microphone amplifier to the normal or the muted mode. when this bit is a 1, the amplifier is muted. see the paragraph entitled amicrophone amplifier, muteo elsewhere in this document. attenuator range: bit b5 is used to select the attenuator range. when it is a 0, the range is 53 db (from full aono to full aoffo). when it is a 1, the range is 27 db. the 53 db range is used for the majority of applications, such as desktop speakerphones (home or office use), intercom units, and any application where the speaker and microphone are in close proximity. the 27 db range is commonly used in european speakerphone applications, where the typical design involves using the handset for the microphone function, and is therefore somewhat separated from the speaker. operating mode: bits b7 and b6 set the circuit operating mode. when 00, the normal voice activated switching is enabled, and the circuit responds to the speech levels as described elsewhere in this document. when 01, the circuit is forced to the receive mode in that the receive attenuator is aono and the transmit attenuator is aoffo. the volume control (bits b3b0) is effective in this mode. when 10, the circuit is forced to the idle mode. when 11, the circuit is forced to the transmit mode. the volume control bits have no effect in the idle or transmit modes. the eight bits are entered serially, b7 first and b0 last. each bit is entered on a clock rising edge. the maximum clock and data rate is 1.0 mhz, and there is no minimum required speed. data ready, which is normally high, is to be held low while the eight bits are clocked in. the eight bits take effect when data ready is taken high. there is no chip address, or other protocol or handshaking required. see figure 2 for a timing diagram. note that data ready need not be taken low before the first clock rising edge. it must be taken low before the first clock falling edge which follows the first clock rising edge. this allows data ready to be taken low coincident with the first clock rising edge, if desired, as well as before that. it is recommended that dr be kept high when not entering data, to prevent disruption of the circuit by transients or glitches on the clock or data lines. this is not required, and dr may be taken low after latching in data, if desired. the clock input can be stopped after b0 is entered, or it may continue to run as long as data ready is taken high before the next clock rising edge. it is recommended that the clock not be continued to prevent possible noise problems. the three inputs must be kept within the range of v cc and gnd. if an input is taken more than 0.5 v above v cc or below gnd excessive currents will flow, and the device's operation will be distorted. see figure 18 for input current requirements at these pins. power on reset the power on reset, when at a logic low (below its threshold of 1.2 v) resets the internal registers to a logic 0, independent of the clock, data, or data ready position. a capacitor on this pin provides a power up time delay to allow v cc to stabilize before the registers can accept data. alternately, pin 20 can be driven directly from a logic source if desired. the por input must be kept within the range of v cc and gnd. if the input is taken more than 0.5 v above v cc or below gnd excessive currents will flow, and the device's operation will be distorted. the configuration of this pin is shown in figure 33. when v cc is applied to the mc33218a, the registers will be enabled when the voltage at por exceeds 1.2 v. the time to reach this level depends on the capacitor at por, and v cc , and will not be less than the time shown in figure 20. the actual reset time is affected by the rise time of v cc . any data written to the registers while por is below 1.2 v will not be stored or effective. the nominal dc voltage at por is 1.5 v. the registers may be intentionally reset by external control by pulling por to ground with (for example) an open collector npn transistor. the time to reset is shown in figure 28. when por once again goes high, the registers' data will remain at 0 until new data is entered. old data is not retained. the time required to release the registers after releasing por (by turning aoffo the npn transistor) is shown in figure 20. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 20 motorola analog ic device data if por is driven by an external logic output, its input current requirement is shown in figure 19. figure 33. power on reset pin v cc 5.0 k por cd 96 k microphone amplifier, mute the microphone amplifier (pins 21, 22) has the noninverting input internally connected to v b , while the inverting input and the output are pinned out. unlike most opamps, the amplifier has an allnpn output stage, which maximizes phase margin and gainbandwidth. this feature ensures stability at gains less than unity, as well as with a wide range of reactive loads. the open loop gain is typically 80 db (f <100 hz), and the gainbandwidth is typically 1.5 mhz. the maximum output swing, for 1.0% or less distortion, is determined by the input capability of the transmit attenuator (300350 mvrms), and by v cc at low supply voltages (see figure 16). the output impedance is <10 w until current limiting is reached (typically 2.0 ma peak). the input bias current at mci is typically 30 na out of the pin. the mute function, when activated, will reduce the gain of the amplifier by shorting the external feedback resistor (rmf figure 34). the amplifier is not disabled in this mode mco remains a low impedance output, and mci remains a virtual ground at v b . the amount of muting (the change in gain) depends on the value of the external feedback resistor, according to the graph of figure 17. muting is enabled by setting bit b4 to a logic 1. figure 34. microphone amplifier and mute v b r mi from microphone from m p r mf mco mci m p interface b4 receive amplifier the receive amplifier (pins 15, 16) has the noninverting input internally connected to v b , while the inverting input and the output are pinned out. unlike most opamps, the amplifier has an allnpn output stage, which maximizes phase margin and gainbandwidth. this feature ensures stability at gains less than unity, as well as with a wide range of reactive loads. the open loop gain is typically 80 db (f <100 hz), and the gainbandwidth is typically 1.5 mhz. the maximum pp output swing, for 1.0% or less distortion, is determined by the input capability of the receive attenuator (300350 mvrms), and by v cc at low supply voltages (see figure 16). the output impedance is <10 w until current limiting is reached (typically 2.0 ma peak). the input bias current at rxi is typically 30 na out of the pin. power supply, v b and chip disable the power supply voltage at pin 24 is to be between 3.5 and 6.5 v for normal operation, and down to 2.7 v with the agc in effect (see agc section). the supply current required is typically 4.6 ma in the idle and transmit modes (at 5.0 v), and slightly more in the receive mode. figure 13 shows the supply current for both the normal and disabled modes. the output voltage at v b (pin 6) is approximately equal to (v cc 0.7)/2, and provides an ac ground for the internal amplifiers, and the system. the output impedance at v b is approximately 600 w , and in conjunction with the external capacitor at v b , forms a low pass filter for power supply noise rejection. the choice of the v b capacitor size is application dependent based on whether the circuit is powered by the telephone line or a regulated supply. see figure 15 for psrr data from v cc to v b . since v b biases the microphone and receive amplifiers, the amount of supply rejection at their outputs is a function of the rejection at v b , as well as the gains of the amplifiers. the amount of current which can be sourced out of the v b pin depends on the v cc voltage (see figure 14). drawing current in excess of that shown in figure 14 will cause v b to drop low enough to disrupt the circuit's operation. this pin can sink 100 m a when enabled, and 0 m a when disabled. the chip disable (pin 8) permits powering down the ic for power conservation. with cd between 0 and 0.8 v, normal operation is in effect. with cd between 2.0 v and v cc , the ic is powered down, and the supply current drops to 110 m a (at v cc = 5.0 v, see figure 13). when cd is high, the microphone and receive amplifiers, the level detectors, and the two attenuators are disabled (their outputs go to a high impedance). the background noise monitors are disabled, and pins 3 and 10 will go to v cc . the v b output, however, remains active, except that it cannot sink any current. the serial port is disabled so that new data may not be entered. upon reenabling the circuit, the 8 internal registers will be set to 0, regardless of their previous contents. figure 26 indicates the disable and enable timing. the cd input must be kept within the range of v cc and gnd. see figure 12 for input current requirements. if the input is taken more than 0.5 v above v cc or below gnd, excessive currents will flow, and the device's operation will be distorted. if the disable function is not used, the pin should be connected to ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 21 motorola analog ic device data applications information switching and response time theory the switching time of the mc33218a circuit is dominated by the components at c t (pin 7, refer to figure 3), and second by the capacitors at the level detector outputs (rlo, tlo). the transition time to receive or to transmit mode from idle, or from the other mode, is determined by the capacitor at c t , together with the internal current sources (refer to figure 29). the switching time is: t v c t i when switching from idle to receive, d v = 150 mv, i = 42 m a, the c t capacitor is 15 m f, and d t calculates to 53 ms. when switching from idle to transmit, d v = 100 mv, i = 42 m a, the c t capacitor is 15 m f, and d t calculates to 36 ms. when the circuit switches to idle, the internal current sources are shut aoffo, and the time constant is determined by the c t capacitor and rt, the external resistor (see figure 29). with c t = 15 m f, and rt = 15 k w , the time constant is 225 ms, giving a total switching time of 0.68 s (for 95% change). the switching period to idle begins when both speakers have stopped talking. the switching time back to the original mode will depend on how soon that speaker begins speaking again. the sooner the speaking starts during the adecay to idleo period, the quicker the switching time since a smaller voltage excursion is required. that switching time is determined by the internal current sources as described above. when the circuit switches directly from receive to transmit (or viceversa), the total switching time depends not only on the components and currents at the c t pin, but also on the response of the level detectors, the relative amplitude of the two speech signals, and the mode of the circuit, since the two level detectors are connected differently to the two attenuators. the rise time of the level detector's outputs (rlo, tlo) is not significant since it is so short. the decay time, however, provides a significant part of the ahold timeo necessary to hold the circuit (in transmit or receive) during the normal pauses in speech. the capacitors at the two outputs must be equal value ( 10%) to prevent problems in timing and signal response. the components at the inputs of the level detectors (rli, tli) do not affect the switching time, but rather affect the relative signal levels required to switch the circuit, as well as the frequency response of the detectors. they must be adjusted for proper switching response as described later in this document. switching and response time measurements using burst of 1.0 khz sine waves to force the circuit to switch among its modes, the timing results were measured and are indicated in figures 2125. a) in figure 21, when a signal is applied to the transmit attenuator only (normally via the microphone and the microphone amplifier), the transmit background noise monitor immediately indicates the apresence of speecho as evidenced by the fact that cpt begins rising. the slope of the rising cpt signal is determined by the external resistor and capacitor on that pin. even though the transmit attenuator is initially in the idle mode (16 db), there is sufficient signal at its output to cause tlo to increase. the attenuator control circuit then forces the circuit to the transmit mode, evidenced by the change at the c t pin. the attenuator output signal is then 6.7 db above the input. with the steady sine wave applied to the transmit input, the circuit will stay in the transmit mode until the cpt pin gets to within 36 mv of its final value. at that point the internal comparator (see figure 32) switches, indicating to the attenuator control circuit that the signal is not speech, but rather it is background noise. the circuit now begins to decay to idle, as evidenced by the change at c t and tlo, and the change in amplitude at tao. when the transmit signal at mco is removed (or reduced), the cpt pin drops quickly, allowing the cpt to quickly respond to any new speech which may appear afterwards. the voltage at c t decays according to the time constant of its external components, if not already at idle. the voltage change at cp2, cpt, and tao depend on the input signal's amplitude, and the components at xdi and tli. the change at c t is internally fixed at the level shown. the timing numbers shown depend both on the signal amplitudes and the components at the c t and cpt pins. b) figure 22 indicates what happens when the same signal is applied to the receive side only. rlo and cpr react similarly to tlo and cpt. however, the circuit does not switch to idle when cpr finishes transitioning since the dial tone detector disables the background noise monitor, allowing the circuit to stay in the receive mode as long as there is a signal present. if the input signal amplitude had been less than the dial tone detector's threshold, the circuit response would have been similar to that shown in figure 21. the voltage change at c t depends on the setting of the volume control (bits b3b0). the +150 mv represent maximum volume. c) figure 23 indicates the circuit response when transmit and receive signals are alternately applied, with relatively short cycle times (300 ms each) so that neither attenuator will begin to go to idle during its aono time. figure 24 indicates the circuit response with longer cycle times (1 s each), where the transmit side is allowed to go to idle. figure 25 is the same as figure 24, except the capacitor at ct has been reduced from 15 m f to 6.8 m f, providing a quicker switching time. the reactions at the various pins are shown. the response times at tao and rao are different, and typically slightly longer than what is shown in figures 21 and 22 due to: the larger transition required at ct pin, the greater difference in the levels at rlo and tlo due to the positions of the attenuators, as well as their decay time, and response time of background noise monitors. the timing responses shown in these three figures are representative for those input signal amplitudes, and burst durations. actual response time will vary for different signal conditions. note: while it may seem desirable to decrease the switching time between modes by reducing the capacitor at ct, this should be done with caution for two reasons: 1) if the switching time is too short, the circuit response may appear to be atoo quicko to the user, who may consider its operation erratic. the recommended values in this data sheet, along with the accompanying timings, provide what f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 22 motorola analog ic device data experience has shown to be a acomfortable responsea by the circuit. 2) the distortion in the receive attenuator will increase as the ct capacitor value is decreased. the extra thd will be most noticeable at the lower frequencies, and at the lower amplitudes. table 1 provides a guideline for this issue. table 1. thd versus ct capacitor ct capacitor idler x transition input @ rai freq. thd @ rao 15 m f 53 ms 20 mvrms 300 hz 1.5% 1.0 khz 0.3% 100 mvrms 300 hz 0.6% 1.0 khz 0.12% 6.8 m f 24 ms 20 mvrms 300 hz 3.6% 1.0 khz 1.0% 100 mvrms 300 hz 1.4% 1.0 khz 0.4% 3.3 m f 12 ms 20 mvrms 300 hz 7.0% 1.0 khz 1.9% 100 mvrms 300 hz 2.8% 1.0 khz 0.7% considerations in the design of a speakerphone the design and adjustment of a speakerphone involves human interfaces issues, as well as proper signal levels. because of this fact, it is not practical to do all of the design mathematically. certain parts of the design must be done by trial and error, most notably the switching response and the ahow does it sound?o part of the testing. among the recommendations for a successful design are: 1) design the enclosure concurrently with the electronics. do not leave the case design to the end as its properties are just as important (just as equally important) as the electronics. one of the major issues involved in a speakerphone design is the acoustic coupling of the speaker to the microphone, which must be minimized. this parameter is dependent entirely on the design of the enclosure, the mounting of the speaker and the microphone, and their characteristics. 2) ensure the speaker is optimally mounted. this fact alone can make a difference of several db in the sound level from the speaker, as well as the sound quality. the speaker manufacturer should be consulted for this information. 3) do not breadboard the circuit with the microphone and speaker hanging out in midair. it will not work. the speaker and microphone must be in a suitable enclosure, preferably one resembling the end product. if this is not feasible, temporarily use some other properly designed enclosure, such as one of the many speakerphones on the market. 4) do not breadboard the circuit on a wirewrapped board or a plugin prototyping board. use a pc board, preferably with a ground plane. proper filtering of the supply voltage, at the v cc pin, is essential. 5) the speakerphone must be tested with the intended hybrid, and connected to a phone line, or phone line simulator. the performance of the hybrid is just as important as the enclosure and the speakerphone ic. 6) when testing the speakerphone, be conscious of the environment. if the speakerphone is in a room with large windows and tile floors, it will sound different than if it is in a carpeted room with drapes. additionally, be conscious of the background noise in a room. 7) when testing the speakerphone on a phone line, make sure the person at the other end of the phone line is not in the same room as the speakerphone. design and adjustment procedure assuming the end product enclosure is available, with the intended production microphone and speaker installed, and the pc boards installed (or temporary substitutes for the pc boards) a recommended sequence is as follows (refer to figure 35): 1) design the hybrid, ensuring it interfaces properly with the phone line for both dc and ac characteristics. the return loss must be adjusted so as to comply with the appropriate regulatory agency. the sidetone should then be adjusted according to the intent of the product. if the product is a speakerphone only, without a handset, the sidetone gain (gst) should be adjusted for maximum loss. if a handset is part of the end product, the sidetone must be adjusted for the minimum acceptable sidetone levels in the handset. generally, for the speakerphone, 1020 db sidetone loss is preferred for gst. 2) check the acoustic coupling of the enclosure (gac in figure 35). with a steady sound coming out of the speaker, measure the rms voltage on the speaker terminals, and the rms voltage out of the microphone. experience has shown that the loss should be at least 40 db, preferably 50 db. this should be checked over the frequency range of 20 hz to 10 khz. 3) adjust the transmit path for proper signal levels, based on the lowest speech levels as well as the loudest. based on the typical levels from commonly available microphones, a gain of about 3545 db is required from the microphone terminals to tip and ring. most of that gain should be in the microphone amplifier so as to make best use of the transmit attenuator, but make sure the maximum attenuator input level at mco is not exceeded. if a signal generator is used instead of a microphone for testing, the circuit can be locked into the transmit mode by grounding cpt (pin 3), or using bits b7 and b6 (set to 11). frequency response can generally be tailored with capacitors at the microphone amplifier. 4) adjust the receive path for proper signal levels, based on the lowest speech levels as well as the loudest. a gain of about 30 db is required from tip and ring to the speaker terminals for most applications (at max. volume). most of that gain should be in the receive amplifier (at rxi, rxo) so as to make best use of the receive attenuator, but make sure the max. attenuator input level at rxo is not exceeded. if a signal generator is used for signal injection during testing, the circuit can be locked into the receive mode by grounding cpr (pin 10), although this is usually not necessary since the dial tone detector will keep the circuit in the receive mode. as an alternate, bits b7 and b6 can be set to 01. frequency response can generally be tailored with capacitors at the receive amplifier. 5) check that the loop gain (i.e., the receive path gain + acoustic coupling gain + transmit path gain + sidetone gain) is less than 0 db over all frequencies. if not, asingingo will occur a steady oscillation at some audible frequency. 6) a) the final step is to adjust the resistors at the level detector inputs (rli and tli) for proper switching response f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 23 motorola analog ic device data (the switchpoint occurs when i 1 = i 2 ). this has to be the last step as the resistor values depend on all of the above adjustments, which are based on the mechanical, as well as the electrical, characteristics of the system. note: an extreme case of level detector misadjustment can result in amotorboatingo. in this condition, with a receive signal applied, sound from the speaker enters the microphone, and causes the circuit to switch to the transmit mode. this causes the speaker sound to stop (as well as the sound into the microphone), allowing the circuit to switch back to the receive mode. this sequence is then repeated, usually, at a rate of a few hz. the first thing to check is the acoustic coupling, and then the level detector input resistors. b) starting with the recommended values for r 1 and r 2 (in figure 3), hold a normal conversation with someone on another phone. if the resistor values are not optimum, one of the talkers will dominate, and the other will have difficulty getting through. if, for example, the person at the speakerphone is dominant, the transmit path is overly sensitive, and the receive path is not sensitive enough. in this case, r 1 should be increased, or r 2 decreased, or both. their exact value is not critical at this point, only their relative value. keeping r 1 and r 2 in the range of 2.020 k, adjust them until a suitable switching response is obtained. c) then have the person at the other end of the phone line speak continuously loudly, or connect to a recording which is somewhat strong. monitor the state of the circuit (by measuring the c t versus v b pins, and by listening carefully to the speaker) to check that the sound out of the speaker is not attempting to switch the circuit to the transmit side (through acoustic coupling). if it is, increase r 1 (at tli) in small steps just enough to stop the switching (this desensitizes the transmit side). if r 1 has been changed a large amount, it may be necessary to readjust r 2 . if this cannot be achieved in a reasonable manner, the acoustic coupling is too strong. d) then have the person at the speakerphone speak somewhat loudly, and again monitor the state of the circuit, primarily by having the person at the other end listen carefully for fading. if there is obvious fading of the sound, increase r 2 so as to desensitize the receive side. increase r 2 just enough to stop the fading. if this cannot be achieved in a reasonable manner, the sidetone coupling is too strong. e) if necessary, readjust r 1 and r 2 , relative to each other, a small amount to further optimize the switching response. microprocessor interface the microprocessor interface (pins 1719) can be controlled by any microprocessor with an spi port, or from a general purpose port which can be configured to provide the correct signals. the mc33218a requires one 8bit word to set the various parameters there is no chip address, or other protocol or handshaking required. see figure 2 for a timing diagram. the function of each of the bits is described in the functional description, as well as in a table near the beginning of this document. the pin's functions are as follows: data: bit b7 is entered first, and b0 last, and each bit is entered on a clock rising edge. the minimum setup and hold times indicated in the electrical characteristics must be adhered to. if more than 8 bits are entered, the last 8 bits to be entered will be stored in the registers. clock: the clock enters the data on each rising edge. there is no minimum required frequency, and the maximum frequency is 1.0 mhz. it is recommended that the clock be stopped when data is not being entered to minimize the possibility of creating audible noise in the speech paths. this input is disabled when data ready is high. data ready: this input must be held low while data is being entered, and then taken high to latch in the new data. the new data will not affect the mc33218a until data ready is taken high. it is recommended that data ready be kept high at all times except when entering data, although this is not required for the ic to function correctly. figure 35. basic block diagram for design purposes acoustic coupling control hybrid g st (g ac ) v 1 tip ring r 1 v 2 r 2 r x attenuator v m mci mike amp speaker amp rao mco tao i 1 i 2 rxo rxi tli rli t x attenuator v b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 24 motorola analog ic device data upon powering up the mc33218a, or when the ic is disabled by means of the cd pin (pin 8), the eight registers are internally set to a logic 0, regardless of their previous contents. this default condition corresponds to normal voice switched operation, 53 db attenuator range, active microphone amplifier, and maximum receive volume level. the amplitude of the three inputs must be less than 0.8 v for a logic 0, and between 2.0 v and v cc for a logic 1. the three inputs must be kept within the range of v cc and gnd. if any input is taken more than 0.5 v above v cc or below gnd excessive currents will flow, and the device's operation will be distorted. power on reset the power on reset function sets the 8 internal registers to logic 0's whenever the mc33218a is powered up, or whenever the chip disable pin (pin 8) is taken high. a capacitor on pin 20 (por) creates a time delay, allowing v cc to stabilize before the registers can accept data. the effective resistance at this pin, for timing purposes, is 115 k w . a 0.1 m f capacitor, for example, provides a time delay of 3.7 ms (at v cc = 5.0 v). alternately, pin 20 can be driven directly from a logic source if desired, the switching threshold is 1.2 v. when taken low, the registers are reset to 0, independent of the clock or data ready position. the por input must be kept within the range of v cc and gnd. if the input is taken more than 0.5 v above v cc or below gnd excessive currents will flow, and the device's operation will be distorted. see figure 33 for the circuit configuration. transmit/receive detection priority although the mc33218a was designed to have an idle mode such that the transmit side has a small priority (the idle mode position is closer to the full transmit side than the receive side), the idle mode position can be moved with respect to the transmit or the receive side. with this done, the ability to gain control of the circuit by each talker will be changed. by connecting a resistor from c t (pin 7) to ground, the circuit will be biased more towards the transmit side. the resistor value is calculated from: r r t v b v 1 where r is the added resistor, r t is the resistor normally between pins 6 and 7 (typically 15 k w ), and d v is the desired change in the c t voltage at idle. v b is the voltage at pin 6. by connecting a resistor from c t (pin 7) to v cc , the circuit will be biased towards the receive side. the resistor value is calculated from: r r t v cc v b v 1 r, r t , d v, and v b are the same as above. switching response and the switching time will be somewhat affected in each case due to the different voltage excursions required to get to transmit and receive from idle. for practical considerations, the d v shift should not exceed 50 mv. disabling the idle mode in order to test the gain, and performance, of the transmit path and the receive path, they can each be set to their full aono positions using bits b7 and b6 of the serial port. however, if it is desired to tests these paths with the ic in the normal voice switched mode (b7, 6 = 00), the transmit or receive attenuator can be set to the aono position, even with steady signals applied, by disabling the background noise monitors. grounding the cpt pin will disable the transmit background noise monitor, causing the circuit to stay in the full transmit mode, even with a low level continuous signal applied to the transmit path. grounding cpr does the same for the receive path. additionally, the receive background noise monitor is automatically disabled by the dial tone detector whenever the receive signal exceeds that detector's threshold. dial tone detector threshold the threshold for the dial tone detector is internally set at 20 mv (14 mvrms) below v b (see figure 31). that threshold can be changed if desired by changing the dc bias level at rxo. since the attenuator input is dc coupled to the receive amplifier, the threshold is changed by forcing an offset through the receive amplifier. as shown in figure 36, connect a resistor (rto) from the summing node to either ground or v cc , depending on whether the dial tone detector threshold is to be increased or decreased. rf and ri are the resistors normally used to set the receive audio gain. figure 36. adjusting dial tone detector threshold ri signal input 100 k rxo rto v cc or gnd v b v b rxi rf to attenuator control circuit v b 20 mv attenuator adding rto, and connecting it to ground will shift rxo up, thereby increasing the dial tone detector threshold. in this case, rto is calculated from: rto v b rf v v b is the voltage at pin 6, and d v is the amount that the detector's threshold is to be increased. for example, if v b = 2.2 v, rf = 10 k, and d v = 20 mv, rto calculates to 1.1 m w . connecting rto to v cc will shift rxo down, thereby decreasing the dial tone detector threshold. in this case, rto is calculated from: rto ( v cc v b ) rf v for example, if v cc = 5.0 v, v b = 2.2 v, rf = 10 k, and d v = 10 mv, rto calculates to 2.8 m w . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 25 motorola analog ic device data board layout, rfi interference although the mc33218a is meant to be used at audio frequencies, the various amplifiers within have bandwidths exceeding 1.0 mhz, and can therefore oscillate due to stray capacitance and other parasitics if care is not taken in the board layout. a pc board, with a ground plane, is recommended for breadboarding as well as production. factors to keep in mind are: the heavy current draw in a speakerphone type product is in the speaker, and consequently, in the speaker amplifier. the power supply and ground connection to the speaker amplifier must be done with care so as to not create significant ripple, or ground noise, for the remaining circuitry. the power supply bypass for the mc33218a should be 100 m f if powered by a regulated power supply, and 1000 m f if powered by the phone line. the bypass capacitor must be physically close to the ic preferably within one inch. this is particularly important in a circuit powered by the phone line. oscillations, or instabilities, can result if this guideline is not followed. as with any circuit which involves mixing analog and digital circuitry, care must be taken in the layout to prevent digital noise from getting into the analog speech paths. as a general rule, all the analog circuitry (phone line interface, speech network, speakerphone, and speaker amplifier) should be ain its own areao. mixing of the analog and digital circuits can result in the high speed logic transitions creating frequencies in the audible range. generally it is not necessary to have a separate analog and digital ground. with many mixed mode devices (such as the mc33218a), this is impractical since there is only one ground pin on the ic. the significant factors here are that the ground plane be continuous, the various circuit sections be arranged logically, and that the v cc distribution be done so as to not distribute noise to the analog circuits. potential radio frequency interference (rfi) problems should be addressed early in the electrical and mechanical design of the speakerphone. rfi may enter the circuit through tip and ring, through the microphone wiring to the microphone amplifier (this wiring should be short), or through any of the pc board traces. the most sensitive pins on the mc33218a are the inputs to the level detectors (rli, tli, xdi) since, when there is no speech present, the inputs are high impedance and these op amps are in a near open loop condition. the board traces to these pins should be kept short, and the resistor and capacitor for each of these pins should be physically close to the pins. all other input pins should also be considered sensitive to rfi signals. in the final analysis ... proper operation of a speakerphone is a combination of proper mechanical (acoustic) design as well as proper electronic design. the acoustics of the enclosure must be considered early in the design of a speakerphone. in general, electronics cannot compensate for poor acoustics, low speaker quality, low microphone quality, or any combination of these items. proper acoustic separation of the speaker and microphone is essential. the physical location of the microphone, along with the characteristics of the selected microphone, will play a large role in the quality of the transmitted sound. the microphone and speaker vendors can usually provide additional information on the use of their products. in the final analysis, the circuit will have to be fine tuned to match the acoustics of the enclosure, the specific hybrid, and the specific speaker and microphone selected. the components shown in this data sheet should be considered as starting points only. the gains of the transmit and receive paths are easily adjusted at the microphone and receive amplifiers, respectively. the switching response can then be fine tuned by varying (in small steps) the components at the level detector inputs (tli, rli) until satisfactory operation is obtained for both long and short lines. for additional information on speakerphone design please refer to the bell system technical journal, volume xxxix (march 1960, no. 2). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 26 motorola analog ic device data definitions attenuation a decrease in magnitude of a communication signal, usually expressed in db. bandwidth the range of information carrying frequencies of a communication system. battery the voltage which provides the loop current to the telephone from the co. the name derives from the fact that cos have always used batteries, in conjunction with ac power, to provide this voltage. cmessage filte r a frequency weighting which evaluates the effects of noise on a typical subscriber's system. central office abbreviated co, it is a main telephone office, usually within of a few miles of its subscribers, that houses switching gear for interconnection within its exchange area, and to the rest of the telephone system. a co can handle up to 10,000 subscriber numbers. co see central office. codec coder/decoder in the central office, it converts the transmit signal to digital, and converts the digital receive signal to analog. db a power or voltage measurement unit, referred to another power or voltage. it is generally computed as: 10 x log (p 1 /p 2 ) for power measurements, and 20 x log (v 1 /v 2 ) for voltage measurements. dbm an indication of signal power. 1.0 mw across 600 w , or 0.775 vrms, is defined as 0 dbm. any other voltage level is converted to dbm by: dbm = 20 x log (vrms/0.775), or dbm = [20 x log (vrms)] + 2.22. dbmp indicates dbm measurement using a psophometric weighting filter. dbrn indicates a dbm measurement relative to 1.0 pw power level into 600 w . generally used for noise measurements, 0 dbrn = 90 dbm. dbrnc indicates a dbrn measurement using a cmessage weighting filter. dtmf dual tone multifrequency. it is the atone dialingo system based on outputting two nonharmonic related frequencies simultaneously to identify the number dialed. eight frequencies have been assigned to the four rows and four columns of a keypad. four wire circuit the portion of a telephone, or central office, which operates on two pairs of wires. one pair is for the transmit path, and one pair is for the receive path. full duplex a transmission system which permits communication in both directions simultaneously. the standard handset telephone system is full duplex. gain the change in signal amplitude (increase or decrease) after passing through an amplifier, or other circuit stage. usually expressed in db, an increase is a positive number, and a decrease is a negative number. half duplex a transmission system which permits communication in one direction at a time. cb radios, with apushtotalko switches, and voice activated speakerphones, are half duplex. hookswitch a switch, within the telephone, which connects the telephone circuit to the subscriber loop. the name derives from old telephones where the switch was activated by lifting the receiver off and onto a hook on the side of the phone. hybrid a twotofour wire converter. idle channel noise residual background noise when transmit and receive signals are absent. line card the pc board, and circuitry, in the co or pbx which connects to the subscriber's phone line. a line card may hold circuitry for one subscriber, or a number of subscribers. longitudinal balanc e the ability of the telephone circuit to reject longitudinal signals on tip and ring. longitudinal signals common mode signals. loop the loop formed by the two subscriber wires (tip and ring) connected to the telephone at one end, and the central office (or pbx) at the other end. generally it is a floating system, not referred to ground, or ac power. loop current the dc current which flows through the subscriber loop. it is typically provided by the central office or pbx, and ranges from 20120 ma. mute reducing the level of an audio signal, generally so that it is inaudible. partial muting is used in some applications. off hook the condition when the telephone is connected to the phone system, permitting the loop current to flow. the central office detects the dc current as an indication that the phone is busy. on hook the condition when the telephone is disconnected from the phone system, and no dc loop current flows. the central office regards an on hook phone as available for ringing. pabx private automatic branch exchange. in effect, a miniature central office, it is a customer owned switching system servicing the phones within a facility, such as an office building. a portion of the pabx connects to the bell (or other local) telephone system. power supply rejection ratio the ability of a circuit to reject outputting noise, or ripple, which is present on the power supply lines. psrr is usually expressed in db. protection, primary usually consisting of carbon blocks or gas discharge tubes, it absorbs the bulk of a lightning induced transient on the phone line by clamping the voltages to less than 1500 v. protection, secondary usually located within the telephone, it protects the phone circuit from transient surges. typically, it must be capable of clamping a 1.5 kv surge of 1.0 ms duration. pulse dialing a dialing system whereby the loop current is interrupted a number of times in quick succession. the number of interruptions corresponds to the number dialed, and the interruption rate is typically 10 per second. the old rotary phones, and many new pushbutton phones, use pulse dialing. receive path within the telephone it is the speech path from the phone line (tip and ring) towards the receiver or speaker. ren ringer equivalence number. an indication of the impedance, or loading factor, of a telephone bell or ringer circuit. an ren of 1.0 equals 8.0 k w . the bell system typically permits a maximum of 5.0 ren (1.6 k w ) on an individual subscriber line. a minimum ren of 0.2 (40 k w ) is required by the bell system. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 27 motorola analog ic device data return loss expressed in db, it is a measure of how well the telephone's ac impedance matches the line's ac characteristic impedance. with a perfect match, there is no reflected signal, and therefore infinite return loss. it is calculated from: rl 20 log ( z line z ckt ) ( z line z ckt ) ring one of the two wires connecting the central office to a telephone. the name derives from the ring portion of the plugs used by operators (in older equipment) to make the connection. ring is traditionally negative with respect to tip. spi serial port interface. a three line microprocessor interface port which is used to clock in data serially. the three lines are clock, data, and a control line which enables entry of the data. some serial ports are bidirectional. sidetone rejection the rejection (in db) of the reflected signal in the receive path resulting from a transmit signal applied to the phone, and phone line. slic subscriber line interface circuit. it is the circuitry within the co or pbx which connects to the user's phone line. subscriber the customer at the telephone end of the line. subscriber line the system consisting of the user's telephone, the interconnecting wires, and the central office equipment dedicated to that subscriber (also referred to as a loop). tip one of the two wires connecting the central office to a telephone. the name derives from the tip of the plugs used by operators (in older equipment) to make the connection. tip is traditionally positive with respect to ring. transmit path within the telephone it is the speech path from the microphone towards the phone line (tip and ring). two wire circuit refers to the two wires connecting the central office to the subscriber's telephone. commonly referred to as tip and ring, the two wires carry both transmit and receive signals in a differential manner. twotofour wire converter a circuit which has four wires (on one side) two (signal and ground) for the outgoing signal, and two for the incoming signal. the outgoing signal is sent out differentially on the two wire side, and incoming differential signals received on the two wire side are directed to the receive path of the four wire side. additional circuit within cancels the reflected outgoing signal to keep it separate from the incoming signal. voiceband that portion of the audio frequency range used for transmission across the telephone system. typically it is 3003400 hz. suggested vendors microphones primo microphones inc. bensenville, il 60106 180076primo telecom transformers microtran co., inc. stancor products valley stream, ny 11528 logansport, in 46947 5165616050 2197222244 (ask for application bulletin f232) prem magnetics, inc. mchenry, il 60050 8153852700 motorola does not endorse or warrant the suppliers referenced. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc33218a 28 motorola analog ic device data dw suffix plastic package case 751e04 issue e outline dimensions p suffix plastic package case 72403 issue d notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 notes: 1. chamfered contour optional. 2. dimension l to center of leads when formed parallel. 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. a b 24 13 12 1 t seating plane 24 pl k e f n c d g m a m 0.25 (0.010) t 24 pl j m b m 0.25 (0.010) t l m note 1 dim min max min max millimeters inches a 1.230 1.265 31.25 32.13 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.020 0.38 0.51 e 0.050 bsc 1.27 bsc f 0.040 0.060 1.02 1.52 g 0.100 bsc 2.54 bsc j 0.007 0.012 0.18 0.30 k 0.110 0.140 2.80 3.55 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 81354878488 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://motorola.com/sps mc33218a/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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